1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the control of program instruction scheduling within data processing systems.
2. Description of the Prior Art
It is known to provide data processing systems, such as superscalar processors and out-of-order processors, which include scheduling circuitry for controlling the issue of program instructions within a stream of program instructions to the execution units which are to perform the corresponding data processing operations. As an example, a superscalar processor may have multiple adder circuits which are capable of performing respective different add operations in parallel and to which different add instructions within a stream of program instructions may be issued in parallel. Out-of-order systems seek to improve the efficiency of use of the processing resources within a processor by modifying the order in which instructions are issued to the execution units away from the order of the stream of program instructions.
It is known from International Published Patent Application No. WO-A-2004/084072 to provide data processing circuits, including processing pipelines, that include error detecting circuitry associated with latches within the pipeline so as to identify errors in a captured signal value. The error detecting circuitry can operate by detecting any change in a signal value following a sampling point at which the signal was captured into a latch. Such a late change in the signal value indicates that the signal value may not have reached its proper value at the point at which it was sampled and accordingly an error has arisen. When such an error is detected, an error recovery response may be initiated, such as flushing the pipeline, adjusting an operational parameter and re-executing the flushed program instructions.
A problem which can arise with such error detecting mechanisms is where a change in a signal value is detected as a result of a signal path through the execution unit which is too quick and results in a change in the signal value consequent on the correct processing of the following cycle thereby resulting in a false positive error detection. Such errors can be termed “short path” errors.
One way of dealing with such short path errors is to identify all possible signal paths through the execution unit which may be traversed during the error detecting period following the sampling/capture time and adding to these paths buffer circuits to slow such propagation such that no change will occur in the signal detected by the error detecting circuitry until after the error detecting period has expired. Whilst such an approach may be effective in suppressing short path errors, it suffers from the disadvantage of requiring the use of additional gates to provide the buffering and also additional analysis seeking to identify short paths which require buffering.